Bistable circuit



Oct. 4, 1960 N. RAvl-:R

BISTABLE CIRCUIT Filed March 4, 195s nited States Patent national Telephone and Telegraph ICorporation, Nutley, NJ., a corporation of Maryland Filed Mar. 4, 1958, Ser. No. 719,082 9 Glaims. (Cl. 307-885) This invention relates to -bistable circuits and in particular to a bistable circuit having a relatively high power output.

The bistable circuit, popularly called p ops, which are lnow commonly found in many data processing and control circuit arrangements are generally some version of the originalV Eccles-Jordan circuit. rIihese circuits comprise a pair of tubes or transistors having the output element of a first tube or transistor interconnected with the control element of the second tube or transistor by a network of resistances and capacitances. 'Iihe resistancecapacitance time constant developed in the network enables a sharp trigger pulse to drive both electron conducting devices below cut off and permits the capacitance discharge race to be won by the tube or transistor which had been non-conducting when the circuit received the trigger pulse. Therefore, one of the tubes or transistors is conducting at any instant and the other tube sistor is cut off.

The iiip ops, described above, have some inherent disadvantage'for certain operations. For instance, because the transition from one stable state to another depends upon a capacitance discharge race, there is a certain `loss of time in the transition. Secondly, these flip flops usually have to be coupled to some type of buffer circuit in order to obtain large power outputs. This becomes apparent if we consider that generally speaking in data processing arrangements there are switching circuits which constitute thev decision circuits and static logic circuits which develop sequential signals. An example of such an arrange- Vment would be a set of counting flip yiiop coupled to a diode decoding matrix which in turn is coupled to other iiip flops. in order to drive the logic circuits, such as the or tranabove diode decoding matrix, it is necessary to develop suitable power at some impedance level. Obviously, the most eicient arrangement is one in which: there is impedance match of the logical circuits. Usually an arnplier is added to the output of the flip flops, but, since the output impedance of the driving amplifier is restricted,

effecting an impedance match is diiiicult. Moreover, the voltage level required for driving the logical circuits, such as the d-iode decoding matrix, puts further restrictions on the amplifier design especially with respect to etiiciency. The addition of the amplifier to the iiip flops provides some impedance match and provides for a reasonable output gain, but it is apparent that an arrangement which might provide for proper impedance matching and proper voltage level requirements would be highly desirable.

It is therefore an object of this invention to provide an improved bistable circuit.

It is a further object of this invention to provide an improved bistable circuit which is not dependent on a sharp trigger pulse.

It is a further object of this invention to provide an improved bistable circuit which is capable of providing large power outputs with high operation efiiciencies.

It is a further object of the present invention to provide a plurality of bistable devices arranged to form a binary counter.

Patented Oct. 4, 1960 i ice another input of the control gate to permit the alternating current to be fed to the respective base element when the gate is opened by the control signal, therebyA enabling the two transistors to conduct in a push-pull operation, representing one of the two stable states of the bistable circuit.

In Iaccordance with another main feature, the present invention provides a transformer being coupled to the outputs of the two transistors to produce an amplification of the outputs and provides rectification means to provide two direct current outputs having a positive and negative polarity.' n

In accordance with another feature working in conjunction with the above features, the present invention provides a feedback circuit from each of the Vdirect current outputs to the control signal input' to enable the bistable circuit to conduct as long yas the direct current output is not terminated.

The above mentioned and other features and objects of this invention will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, in which:

Fig. l is a schematic diagram of a two stage binary counter in accordance with the invention; Y

Fig. 2 is a graph of the clock pulse train and the output pulses of the two stages shown in a relative time relation.

The common connection of the two base elements and the diodes is coupled to a resistor 20 which is series coupled to B+. The emitterelements 21 and 22, respectively, of each transistor 13l and 14 are respectively connected to ground. The collector elements 23 and 24 of the transistors 13 and 14 are respectivelyv coupled to the primary transformer windings 25 and 26. The primary .windings 25 and 26 yare coupled to the same core as the secondary windings Z7 and 28 as indicated in Fig. l by the core designated C. 'l'fhe secondary windings 27 and 28 are center tapped to ground. The secondary winding 27 has a pair of diodes Z9 and 30 connected in parallel across the terminals of the winding and biasedV in a forward direction to the center gro-und tap.r 'I'he secondary -winding 28 has a pair of diod 31 and 32 connected in parallel across the terminals of the winding and biased in a forward direction 4away from the center ground tap'. Each of the last-mentioned parallel connections ofthe secondary windings 27 and 28 is respectively connected to a parallel resistance-capacitance circuit 33 and 34. By way of illustration the'parallel resistance-capacitance circuit 33 is connected to a minus 3 volts reference and circuits 37 and 38 respectively are coupled'to B+ through the respective associated resistances 39 and 40 and each gating circuit 37 and 3S respectively bas a second input -terminalat 41'-and 42. Theoutputs of the gating cir- Lcarits`37 /andv38 are-respectively connected-to the'input 'ofvan or. gate 43. TheV output 4of the for gate 43 is coupled to-Athecoutrolainput terminal 16. fille-components Vofthe secondi-stage -12 vare-identical except that --thefre are two vadditional inputs 44 and 45:to :respectively condition on the andgates 46-and 47 which are thecounterparts 'of 1the an "fvga'tes 3-7 and 38 in the first stage 1-1. Inadditionthere Jis'a'tl'n'rd fandf -gate -46q whichis Icouplerleinparalleltothe output 51. The @positive direct fcurrent Aoutput terminal 3-5 -connected tothe-input terminal `45 while `the lnegative direct current ,outputjterminalwis coupled--to-the input terminal-44. VIn Fig. 2 the waveform 48 shows the clockpulse train ghaving afnegativeandspositive-clockpulse for each time increment. The waveform .49fshows the'output pulse 'frei-nahe output terminal 35 and waveform 50 shows .theoutput pulse from the output terminal 51 of the second 'stage.

Considering Fig. l in connection with the operation of -theT invention, there-is vv.af-clockY pulse train, 'suchvas 'that shown -by vthe-waveforms 48, being fed to the terminals -41 and -42 of the-.gatesand 38. The 'terminal 41Vreceives the 'negative pulses 'ofthe clock trainsuchV as 48a of Fig.

. 2;and the terminal '42- receives the positive pulses such asV 4811 of Fig. 2.. The two states of Athe bistable circuit'll "fare-:the first state, Vwhen" the-transistors 13'and '14are l:amplifying the L'alternating-f current input; `and thel second -vstate, when'the transistors v13 yand 14 are "substantially non-conducting. Assumingthetransistors 13 Vand 14 are mori-conducting, orv in the second stable state, the point 35 is at a substantially'negative; potential with respect i-togroud. `The point 35 iisft thisfsubstantiallynegative ,potential Vbecause lof the resistor divider ynetwork includ- =ingfther`esistors39, 39a2and 53. With'` point 35'being at af substantially negative potential, theV input 52 Vof 'the agate-+43 is likewise at a substantially negative potential. .-During' Vthis same' time the point 36 is 'at-a positive potenftialffwith'respect tov ground by propenproportioning of the valuesofv the `resistors, particularly/"40 and 53. Al-

-"When the clock pulse tain48 is' 'passed to the terminals l "41'and'42, the negative pul'sesfat' 41 continue to' hold 'the"foutput` voltage from gate"37 negative; therefore, the 'input -termin'al'52 remainsfat afsubstantially negative potential. -When 'the positive pulses are'applied Yto the v'te'rrninall42, the output voltage from the' gate'38 is lifted "5to the' peak of the positive"potential pulse which vin' turn -liftsvthe potential ofthe output of gate 43 by increased 'conduction across the `resistance '53. "With theinput potential f thev'gate 43 lifted kto av substantially high-po- -te'iitir'the gate'is is opened'tojpermif the 'alternating currentto be eiectivelyreceived' at thetransistors 13 r'14. `Prior lto Lthe change Aof the-potential level at '5the"' ga`te`43 bythe clock pulses, 'the output of gate Vv1.5

Y Y was held lat a substantially negative potential. With the jgate V"15 being lheld Aat thissub'stantially negative potential, `the"alternatingcurrent whichwas being applied to the basefel'ements of'eahofthetransistors'13 and 14 was fblocked at diode 19, which subsequently became unblocked.

"'With `thegatefS open described above' the alter- `fnating 'current is amplified bythe transistors13 and 14 'fandgtliefPNP transistor" 13"conducts' during the negative of the cycle While 'thez'N-PN transistor 14 fconducts -during"the'postivehalf of the'A.C. cycle to provide a "pushpll operation of these symmetrically' coupled tranvfs i "st'o`rs. ,'I'hoprimry "windings :25" and VQ26 are coupled 'to thefame vcorefasthe vsecondary windings' 27 and 28.

'46a-has Aone'of its two Vinputs conditionednegatively since 4By couplingathesoutputs ,at'35f'and .-36 through'the connecting leads-34 .and 35S-to 'thelfORe-gate 43,1 there fis, :provided a feedback arrangement totthecontrwolzgate 15. In other wordsrwithlthetransistors amplifying the alternating cu'rreiitinputaidtherefore providing a positive output at 35 Whennhernegative clo'okfpulse at 41 terminates, the input lead 52 of the OR gate 43 will remain at the high potential of 35 and therefore lift or hold t'ne :gate -43^at the vhighpotential that originally-opened the gate 1S. During .this `salme conducting operation, as stated before, the output terminal 36 is held negative :because there-'fis substantial electron flow across the. RC circuit-.34 :in the' direction. of? the |3 reference voltage. Since the outputterminalr36i-is held negative, thengate V38is 1likewisenega`tive,and,l therefore, the input lead-.56

of the'gatei43 vappears-with a negative potential -while the transistorslare1conducting.

)At thextimeithatthefnext pair ofv clock pulsesarrives Yat .the-terminals 241'fa'nd v"42 the negative Vpulse ,at 4I Vwill-:causethe gatel37 to become negative and therefore render the inputlead 52 negative; While the' positive;pulse received atf42 will'fail toflifttheipotentialof the'=gate .38 vsince itfwill `be held-:negativeshy the conduction across `the RCicircuit 34 and, therefore, the -input lead 561will remain negative. `With theinputsSZand 56 of the-gate --43 negative, the `gate '43.rrenderslth`einput terminal 16 negative and hence the gate 15 becomesvclosed. When -fthevgate l'Szbecomes closed, the'bistable vdevicevll revertsr-toltbe-secondf stable state "which was initiallyl described, Iwhereinbthe `alternating 'curr'ent' is fno longer Veffectively iapplied to the base 'elements fof the `transistors `transistor -is responsive to--a 4:negative voltage input. 'By `inserting the capacitor and'resistance circu-t'57- as'shown,

the'direct current is blocked' and hence lthereris'no'dis- -sipation of power in thetransformer during-thismo'l condition.

'Considering the operation of Athe second bistabler circuit 12 of the counter in connection with the operation of theiirst bistable circuit 11, the an gate *46 'of the *bistable circuit 12 isl connected tobe further conditioned by the output at 36 of the bistable circuit 11. 'During the time that the transistors 13 and 14Vare conductinggthe terminal 35 isat a positive potential. The and gate y51 is negative. V'vIu'he and gate 46'of theabistable device 12 hasone of'its twolinputs conditonedlnegatively puts conditioned positively by 67 and 35. MrI'he clock `pulse train 48 is likewise applied'to the terminals58 46 at this time ispositive during the clock'perio'd because it is connected to point 36 (A1) and point 51 (A2) 'which is also now positive. The positive pulse't) conditions the third input' totheand gate 47jpositive and thereby'lifts the potential of the or 'gate 62 toa positive potential.

' Withthe' orf gate 62 being liftedto fa positive` potential, `th'e'in'pntt of the gate 64v islikewise'lifted to a positive potential and, therefore, the gate 64 is opened. With the opening of the gate 64, the alternating current input to the transistors 65 and 66 becomes effective, and these transistors amplify the alternating current input in a fashion similar to that described in connection With the bistable circuit 11. The output at 51 will remain a positive direct current voltage and the ouput at 67 will remain a negative direct current voltage as long as the transistors 65 and 66 are conducting and lamplifying the alternating current input.

Examining the waveforms of Fig. 2, it becomes clear that lat the third clock pulse, depicted at 65 and 69, the bistable device 12 will not be affected and the bistable device 11 will be transferred to its rst stable state. This is true because in the off state of the bistable circuit 1'1, the :terminal 36 was positive rendering one input of the gate 46 positive. Since the bistable circuit .12 is conducting at the third clock pulse time, the terminal 51 is positive rendering the gate 46 positive and independent of the clock pulses since they are not applied thereto.

It becomes clear that a counter of any number of stages according to well-known logic may be bui-lt by duplicating the inputs to the counterparts of the and gates 46, 46a and 47 which belong to the added stages, and thereby providing an output in accordance with Well-known binary counting arrangements. The invention has been described using a symmetrically coupled PNP and NPN type transistors. However, a pair of transistors, both of the same type, might be used with an inverter means coupled therebetween to provide for the push-pull arrangement which renders the invention operative with a high eiciency. It also becomes clear upon examination of the invention that the invented circuit provides a means for having a bistable circuit with high power amplification because the alternating current input feature makes stepup or or step-down transformers possible; that the inventive circuit provides high efficiency because of the pushpull arrangement; and that the inventive circuit provides a means of accomplishing a bistable condition with a voltage pedestal rather than sharp trigger pulses. The accomplishment of the changing of the bistable conditions with a voltage pedestal instead of a sharp trigger pulse is apparent in the operation of the circuit since it is only necessary to accomplish .a voltage shift at `the proper and gate to accomplish the subsequent transition from one of the bistable states to the second bistable state.

While I have described above the principles of my invention in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation to the scope of my invention as set forth in the objects thereof and in the accompanying claims.

I claim:

l. A bistable circuit comprising first and second transistors operating in two stable states, a gating circuit having first and second input means, fa clock signal source of regular and opposite polarity pulses coupled to said iirst gating input means, an alternating current signal source of radio frequency signals coupled to said second gating input means, first circuitry means coupling said.

transistors to said gating circuit to render, when said gating circuit is open, said first and second transistors respectively responsive to the negative and positive halves of said alternating current signal input, second circuitry means connecting the respective outputs of said transistors to said iirst gating input means to render said transistors conducting after receiving a iirst clock signal and nonconducting after receiving a second clock signal, said first gating input means including second, third and fourth other terminal opposite the common connection, coupled to a reference voltage.

3. A bistable circuit according to claim 1, wherein said tirst circuitry means includes ra capacitor coupled in series to the base of one of said transistors and a resistance coupled in parallel to this last-mentioned common connection to block the direct current to said transistor to prevent unnecessary power dissipation when said gating circuit is closed.

4. A bistable circuit accordingto claim 1, wherein said clock signal source transmits a clock pulse train havingsimultaneously positiveV and negative characteristics with the positive portion thereof coupled 4to said third gating circuit and negative portion thereof coupled to the fourth gating circuit.

5. A bistable circuit according to claim 4, wherein the output means of each of said transistors includes a single transformer having a pair of primary and secondary windings, said secondary windings each being coupled to an associated rectifying means, the output of said rst secondary winding rectifying means being coupled to said third gating circuit and said second secondary winding rectifying means being coupled toV saidfourth gating means.

6. A bistable circuit comprising a iirst gating circuit having a pair of diodes coupled in parallel to a resistance which in turn is coupled to a iirst reference voltage, a PNP and an NPN transistor symmetrically coupled by said rst gating circuit, a radio frequency signal source coupled to the input of one 4of said first gat-ing diodes,

n or gate comprising a iirst and second diode coupled in parallel to a resistance which in turn is coupled to a second reference voltage, the output of said or gate circuitry coupled to the input of the other of said first gating circuit diodes, a second and third and gate each having a pair of diodes coupled in parallel to a respective resistance each of which is respectively coupled to a reference voltage, a transformer having iirst and second primary windings Iand first `and second secondary windings, said rst primary winding being coupled to the collector element of said PNP transistor and to -a negative reference potential, said second primary Winding being coupled to the collector element of said NPN transistor and a positive reference potential, said rst secondary winding coupled to rectifying means to produce =a positive direct current output therefrom, said second secondary winding coupled to rectifying means to produce a negative direct current output therefrom, a source of clock pulse signals to transmit a clock pulse train having simultaneously pairs of clock pulses respectively `having positive and negative characteristics, said second and gate having the input to one of its diodes coupled to said positive -direct current output and the `other of its diodes coupled to the negative portion of said clock train and sai-d third and` gate having one of its diodes coupled to said negative direct current output and the other of its diodes coupled to the positive portion of said clock pulse to render said transistors conducting in accordance with the radio frequency signal after having received -a first pair of clock pulses and non-conducting after having received a second pair of clock pulses.

7. A binary counter arrangement comprising a plurality of stages, each of said stages including iirst and second transistors, a gating circuit coupled to the control elements of each of said transistors, an alternating current signal source coupled to said gating circuit, a control signal input means coupled to said -gating circuit to render .said gating circuit open and closed with the application of control signals, said transistors respectively conducting in response to the negative and positive halves of said alternating current signal input when said gating circuit is opened, first and second counter output means coupled to the output means 'of each of said transistors to provide simultaneously a positive and a negative direct current output when said transistors are conducting, a,

source of clock pulse signals, a second `sind third gating means respectively coupling said clock pulsesignals with saidk respective cfmnter output mean, second lcircuitry meansk connecting the :respective second and third Y gating output-means to said control signal. inputmeans topfovide'arfeedbackrsignal to said control signal input means when said transistors yare conducting, said transistorsibeing conducting and non-conducting in response toiproper conditioning of said second and third. gating means, third circuitry means couplingvthe iirst counter .outputrmeans of ya lower stage to each -secondgating means of each higher ordered stage, andiourth circuitry means. coupling the .second counter output means of said lowerlrstageto the -rst gating means of.highenorderedstageito render a higher ordered stage conductingand4 n on-conductingin response to a triansition from conducting to non-conducting of said next lower orde-redstages.

8. A -binary counter .arrangement according to claim 7,

wherein `saidtransistors of each stage lare symmetrically coupled PNP and NPNtransistors.

9. A binary counter-arrangementaccording to clairn, wherein said control signal input means includes aV gating circuit having different predetermined nnmbersofinputs for each stage of said counter in accordancewith its numberedorder.

References Cited in the le of this patent UNITED STATES PATENTS 2,756,329 ,.Lubkin d July 24, 1956 2,782,267 Beck Feb. 19, 1957 2,S2Q,897 Dean et al. Jan. 21, 1958 OTHER REFERENCES Richards: Arithmetic Oper-ations yin Digital Computers, 1955, pagesr46 and 47. 

